The TL1549,TLC1591,and TLC1549M are 10-bit,switched-capacitor,successive-approximation(一连近似的)analog-to-digital converters.these devices have two digital inputs and 3-state output [chip select (cs低电平有用) ，input-output clock (I/O clock),and data output (DATA OUT)] that provide a three-wire interface to the serial port of a host processor.
The sample-and-hold function is automatic . The converter incorported in these devices features differentil high-impedance reference inputs that facilitate ratiometric conversion,scaling(比例),and isolation（绝缘） of analog ciruitry from logic and supply noise.a switched-capacitor (转换电容器) design allows low-error converson over th full operating free-air temperature range.
The TLC1549C is characterized for operation from 0度 to 70度 。The TLC15491 is characterized for operation from -40 度 to 85度. The TLC 1549M is characterized for operation over the full military temperature range of -55度 to 125度。
with chip select (cs) inactive (high),I/O clock is initially disabled and DATA OUT is in the high-impedance state. When the serial interface takes cs active (low ),the cnversion sequence begins with the enabling of I/O clock and the removal of DATA OUT from the high-impedance state.the serial interface then provides the I/O clock sequence to I/O clock and receives the previous conversion result fro DATA OUT .I/O clock receives an input sequence that is between 10 and 16 clock long from the host serial interface .the first ten I/O clocks provide the control timing for sampling the analog input.
there are six basic serial interface timign modes that can be used with the TLC1549. These modes are determined by the speed of I/O clock and the operation of cs shown in Table .these modes are(1) a fast mode with a 10 clock transfer and cs inactive (high ) between transfers,(2)a fast mode with a 10-clock transfer and cs active (low) continuously,(3) a fast mode with an 11-to 16 clock transfer and cs inactive (high) between transfes ,(4) a fast mode with a 16-bit transfer and cs active (low) continuously,(5) a slow mode with an 11 - to 16 -clock transfer and cs inactive (high)between transfers,and(6)a slow mode with a 16 -clock transfer and cs active(low)continuously.
The MSB of the previous conversion appears on DATA OUT on the falling edge of cs in mode 1,mode 3,and mode 5,withi 21 us from the falling edge of the tenth I/O clock in mode 2 and mode 4,and following the sixteenth clock falling eddge in mode 6.the remaining nine bits are shifted out on the next nine falling edges of I/O clock .Ten bits of data are transmitted to the host serial intrface through DATA OUT.The number of serial clock pulses used also depends on the mode of operation,but a minimum of ten clock pulses is required for conversion o begin.on the tenth clock falling edge,the internal logic takes DATA OUT low to ensure that the remaining bit values are zero if the I/O clock transfer is more than ten clocks long.